This invention relates, in general, to digital processors, and more particularly, to a method for providing a clear and wait instruction for a digital processor.
In the operation of digital processors it is often desirable to have the digital processor system stop processing instructions and to wait upon an input from an external peripheral device. Often before having the processor system wait upon the external input it is desirable to clear one or more bits in the status or condition code register. In the past, some digital processors had a simple wait instruction which would allow the processor to wait for an external input while yet other processors would stack certain preselected registers and then wait for an external input. In such a situation if it was desired to change or clear a bit in the condition code register then a separate instruction had to be executed to make the change to the contents of the condition code register.
There are disadvantages in a digital processor requiring two separate instructions to perform a clear and wait function. In particular, if a digital processor is executing a clear instruction and an external input or interrupt occurs then upon the completion of the clear instruction, the digital processor will service the interrupt and upon executing the return from interrupt instruction the processor will then execute the wait instruction. However, if the interrupt that was serviced upon the completion of the clear instruction was the interrupt that the machine was being prepared to wait for then the machine would remain in the waiting mode until an operator intervened. One way to avoid such a problem was to extend the clear instruction by one clock cycle so that an interrupt would not be responded to between the clear and the wait instruction. However this solution could create other problems.
Accordingly, it is an object of the present invention to provide a digital processor capable of performing a clear and wait operation in response to a single instruction.